Part IV: Digital Electronics | Chapter 11

Flip-Flops & Counters

SR latch, D, JK, and T flip-flops, timing diagrams, synchronous and asynchronous counters, binary, ring, and Johnson counters

1. SR Latch — The Basic Memory Cell

The SR (Set-Reset) latch is the simplest bistable circuit. Built from two cross-coupled NOR or NAND gates, it has two stable states and forms the foundation of all flip-flop circuits.

S=0, R=0

Q (hold)

No change

S=1, R=0

1 (set)

Output set HIGH

S=0, R=1

0 (reset)

Output reset LOW

S=1, R=1

? (invalid)

Forbidden state

The forbidden state (S=R=1) can lead to metastability — a circuit that takes an indeterminate time to settle. The D flip-flop eliminates this by ensuring S and R are always complementary.

2. Flip-Flop Types

D flip-flop: captures D input on rising clock edge, holds until next rising edge

D Flip-Flop

\( Q_{n+1} = D \)

Data input D is captured on the active clock edge. Most common type; used in registers and pipelines.

JK Flip-Flop

\( Q_{n+1} = J\overline{Q} + \overline{K}Q \)

J=K=1 toggles output — eliminates the SR invalid state. Versatile but slower than D type.

T Flip-Flop

\( Q_{n+1} = T \oplus Q \)

Toggle: when T=1, output flips each clock cycle. Built from JK with J=K=T.

SR Flip-Flop

\( Q_{n+1} = S + \overline{R}Q \)

Clocked SR: edges control when set/reset occur. Forbidden state S=R=1 still exists.

3. Counters

Counters are registers whose state advances through a defined sequence. An N-bit binary counter cycles through \( 2^N \) states. The key distinction is synchronous vs asynchronous:

Synchronous Counter

All flip-flops clocked simultaneously. No ripple delay. Faster and easier to analyze. Used in most modern designs.

\( T_i = Q_0 Q_1 \cdots Q_{i-1} \)

Asynchronous (Ripple) Counter

Each flip-flop clocked by the output of the previous. Simpler to build but introduces cumulative propagation delay (ripple).

\( t_{prop} = N \times t_{FF} \)

Specialty counters include the ring counter (single 1 bit circulating — N states from N FFs) and the Johnson counter (complemented output fed back — 2N states from N FFs, no glitches).

4. Python: 4-Bit Counter & D Flip-Flop Timing Diagram

Simulate a 4-bit synchronous binary counter over 16 clock cycles, plot Q0–Q3 timing waveforms, and show D flip-flop capture behavior with a random data input.

Python

script.py123 lines

import numpy as np
import matplotlib.pyplot as plt
import matplotlib.gridspec as gridspec

plt.style.use('dark_background')
fig = plt.figure(figsize=(14, 11))
fig.patch.set_facecolor('#0a0a0a')
gs = gridspec.GridSpec(3, 1, figure=fig, hspace=0.55)

NUM_CLOCKS = 16

# ---- Generate clock signal ----
t = np.arange(0, NUM_CLOCKS * 2)   # two samples per clock period
CLK = np.tile([0, 1], NUM_CLOCKS)  # square wave

# ---- 4-bit synchronous binary counter ----
# Q[n+1] = Q[n] + 1 on rising clock edge
counter_vals = np.arange(NUM_CLOCKS) % 16   # 0..15 repeating
Q0 = (counter_vals >> 0) & 1
Q1 = (counter_vals >> 1) & 1
Q2 = (counter_vals >> 2) & 1
Q3 = (counter_vals >> 3) & 1

def make_waveform(bits):
    '''Repeat each bit value twice to align with CLK signal.'''
    return np.repeat(bits, 2)

CLK_wave = CLK
Q0_wave  = make_waveform(Q0)
Q1_wave  = make_waveform(Q1)
Q2_wave  = make_waveform(Q2)
Q3_wave  = make_waveform(Q3)
count_wave = make_waveform(counter_vals)
t_wave = np.linspace(0, NUM_CLOCKS, len(CLK_wave))

# ---- Plot 1: Clock and Q bits timing diagram ----
ax1 = fig.add_subplot(gs[0])
ax1.set_facecolor('#0f0f0f')

signals = [
    (CLK_wave,  '#9ca3af', 'CLK',  5.5),
    (Q0_wave,   '#34d399', 'Q0',   4.0),
    (Q1_wave,   '#60a5fa', 'Q1',   2.5),
    (Q2_wave,   '#fbbf24', 'Q2',   1.0),
    (Q3_wave,   '#f87171', 'Q3',  -0.5),
]
for wave, col, lbl, offset in signals:
    ax1.step(t_wave, wave + offset, where='post', color=col, linewidth=1.8, label=lbl)
    ax1.axhline(offset, color=col, linewidth=0.4, alpha=0.3, linestyle=':')
    ax1.text(-0.5, offset + 0.5, lbl, color=col, fontsize=9, va='center', ha='right')

ax1.set_xlim(-0.5, NUM_CLOCKS + 0.2)
ax1.set_ylim(-1.2, 7.5)
ax1.set_xlabel('Clock Cycles', color='#9ca3af')
ax1.set_title('4-Bit Synchronous Binary Counter: Timing Diagram', color='#6ee7b7', fontsize=11)
ax1.tick_params(colors='#9ca3af')
ax1.set_yticks([])
ax1.grid(True, color='#1f2937', axis='x', alpha=0.5)
for sp in ax1.spines.values(): sp.set_edgecolor('#374151')

# Annotate count values
for i in range(NUM_CLOCKS):
    ax1.text(i + 0.5, 7.0, str(i), ha='center', color='#a7f3d0', fontsize=7)

# ---- Plot 2: Counter value as staircase ----
ax2 = fig.add_subplot(gs[1])
ax2.set_facecolor('#0f0f0f')

ax2.step(t_wave, count_wave, where='post', color='#34d399', linewidth=2, label='Counter value')
ax2.fill_between(t_wave, count_wave, step='post', alpha=0.15, color='#34d399')
ax2.axhline(15, color='#f87171', linewidth=1, linestyle='--', alpha=0.6, label='Max = 15')
ax2.set_xlabel('Clock Cycles', color='#9ca3af')
ax2.set_ylabel('Count Value', color='#9ca3af')
ax2.set_title('Counter Value Over 16 Clock Cycles (0 to 15, then wraps)', color='#6ee7b7', fontsize=11)
ax2.set_xlim(0, NUM_CLOCKS)
ax2.set_ylim(-1, 17)
ax2.legend(fontsize=9, framealpha=0.2)
ax2.tick_params(colors='#9ca3af')
ax2.grid(True, color='#1f2937', alpha=0.5)
for sp in ax2.spines.values(): sp.set_edgecolor('#374151')

# ---- Plot 3: D flip-flop timing (D=arbitrary data, Q follows D on rising CLK edge) ----
ax3 = fig.add_subplot(gs[2])
ax3.set_facecolor('#0f0f0f')

# Generate pseudo-random D input
np.random.seed(42)
D_vals = np.random.randint(0, 2, NUM_CLOCKS)
# D flip-flop: Q[n+1] = D[n] on rising clock edge
Q_ff   = np.zeros(NUM_CLOCKS, dtype=int)
for i in range(1, NUM_CLOCKS):
    Q_ff[i] = D_vals[i-1]   # sample D on rising edge

D_wave  = make_waveform(D_vals)
Q_ff_wave = make_waveform(Q_ff)

ax3.step(t_wave, CLK_wave + 3,    where='post', color='#9ca3af', linewidth=1.8, label='CLK')
ax3.step(t_wave, D_wave   + 1.5,  where='post', color='#60a5fa', linewidth=1.8, label='D (data in)')
ax3.step(t_wave, Q_ff_wave + 0.0, where='post', color='#34d399', linewidth=2.0, label='Q (sampled on rising CLK)')

for offset, col in [(3, '#9ca3af'), (1.5, '#60a5fa'), (0, '#34d399')]:
    ax3.axhline(offset, color=col, linewidth=0.3, alpha=0.3, linestyle=':')

ax3.text(-0.5, 3.5,  'CLK', color='#9ca3af', fontsize=9, ha='right')
ax3.text(-0.5, 2.0,  'D',   color='#60a5fa', fontsize=9, ha='right')
ax3.text(-0.5, 0.5,  'Q',   color='#34d399', fontsize=9, ha='right')

ax3.set_xlim(-0.5, NUM_CLOCKS + 0.2)
ax3.set_ylim(-0.5, 5.5)
ax3.set_xlabel('Clock Cycles', color='#9ca3af')
ax3.set_title('D Flip-Flop Timing: Q Captures D on Rising Clock Edge', color='#6ee7b7', fontsize=11)
ax3.set_yticks([])
ax3.tick_params(colors='#9ca3af')
ax3.grid(True, color='#1f2937', axis='x', alpha=0.5)
for sp in ax3.spines.values(): sp.set_edgecolor('#374151')
ax3.legend(fontsize=8, framealpha=0.2, loc='upper right')

plt.suptitle('Flip-Flops & Counters: D Flip-Flop and 4-Bit Binary Counter', color='#6ee7b7', fontsize=13, y=1.01)
plt.savefig('output.png', dpi=130, bbox_inches='tight', facecolor='#0a0a0a')
print('Saved output.png')
print('4-bit synchronous binary counter: counts 0-15 over 16 clock cycles')
print('D flip-flop: Q samples D on every rising clock edge (1-cycle delay)')

Click Run to execute the Python code

Code will be executed with Python 3 on the server

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