Electronics/Part VII: Modern Electronics/PCB Design

Chapter 19: PCB Design

A printed circuit board (PCB) transforms a schematic into a physical assembly of copper, dielectric, and components. Mastering PCB design means understanding how geometry affects signal integrity, how current density limits trace width, how layer stackups control impedance, and how good layout practice eliminates EMC headaches before they arise.

4-Layer PCB Stackup

19.1 Schematic Capture & Component Footprints

PCB design begins in a schematic editor (KiCad, Altium, Eagle) where components are placed as symbols connected by nets. Each symbol is linked to a footprint — the physical pad pattern on the PCB — which must match the land pattern specified in the component datasheet.

Common package families and their footprint considerations:

Through-hole (DIP, TO-220): drill holes with annular rings; excellent mechanical strength; good for high-current or high-voltage parts.
SMD passive (0402, 0603, 0805): two rectangular pads; smaller sizes improve density but increase assembly cost.
Fine-pitch IC (QFP, SOIC, TSSOP): closely spaced gull-wing leads; requires stencil-applied solder paste and reflow soldering.
Area-array (BGA, QFN, LGA): pads beneath the component; requires X-ray inspection; thermal pad on QFN carries heat away.

Design Rule: Courtyard Overlap

Every footprint has a courtyard — the minimum placement clearance boundary. Overlapping courtyards indicate a mechanical collision and will prevent assembly. Always run DRC (Design Rule Check) before layout export.

19.2 PCB Layer Stackup

A 2-layer board (signal top, signal bottom) is the most economical option, suitable for simple designs below ~100 MHz. High-speed digital or RF designs demand a 4-layer stackup: signal, ground plane, power plane, signal. The solid reference planes immediately adjacent to signal layers dramatically reduce loop inductance and radiated emissions.

2-Layer Stack

Top copper (35 µm)Signal + power routing

FR4 core (1.6 mm)ε_r ≈ 4.4

Bottom copper (35 µm)Signal + GND fills

4-Layer Stack

L1 signal (35 µm)High-speed signals

Prepreg (200 µm)ε_r ≈ 4.2

L2 GND planeSolid reference

Core (1.0 mm)FR4

L3 PWR planeSolid power rail

Prepreg (200 µm)ε_r ≈ 4.2

L4 signal (35 µm)Low-speed signals

19.3 Trace Width for Current — IPC-2221

The IPC-2221 standard relates current capacity to trace cross-sectional area and allowed temperature rise. For external traces (top or bottom layer):

\( I = 0.048 \cdot \Delta T^{0.44} \cdot A^{0.725} \)

where \(I\) is current in amperes, \(\Delta T\) is the allowed temperature rise in °C, and \(A\) is the cross-sectional area in square mils (1 mil = 25.4 µm). Inverting for trace width \(W\):

\( W = \frac{1}{t_{\text{Cu}}} \left(\frac{I}{0.048 \cdot \Delta T^{0.44}}\right)^{1/0.725} \)

where \(t_{\text{Cu}}\) is the copper thickness in mils. Internal traces use the coefficient 0.024 (half the current capacity). A practical rule of thumb: 1 A per mm of trace width for 1 oz copper with 10 °C rise.

19.4 Impedance-Controlled Traces

For signals above ~100 MHz (or with rise times below ~1 ns), traces become transmission lines. The characteristic impedance of a microstrip (trace on outer layer above reference plane) is:

\( Z_0 = \frac{87}{\sqrt{\varepsilon_r + 1.41}} \ln\!\left(\frac{5.98\,h}{0.8\,w + t}\right) \)

where \(h\) is dielectric height, \(w\) is trace width, \(t\) is copper thickness (all in consistent units), and \(\varepsilon_r\) is the dielectric constant. For a 50 Ω microstrip on FR4 (ε_r = 4.4) with a 1.6 mm board and 1 oz copper, the required trace width is approximately 3 mm.

A stripline (trace buried between two reference planes) gives better shielding and lower radiation but requires a more expensive stackup. Differential pairs (100 Ω) are used for USB, Ethernet, HDMI, and LVDS signals.

Signal integrity rule: when trace electrical length exceeds λ/10 (wavelength divided by 10), transmission-line effects dominate. At 1 GHz in FR4 (ε_r = 4.4), λ ≈ 143 mm — so traces longer than ~14 mm must be impedance-controlled.

19.5 Via Types

Through-Hole Via

Drilled from top to bottom of the board. The most common type. Minimum drill diameter ~0.2 mm (HDI), typical 0.3–0.8 mm. Every layer must accommodate the drill path, reducing routing channels on inner layers.

Blind Via

Connects an outer layer to one or more inner layers without penetrating the entire board. Enables higher routing density (BGA breakout). Requires sequential lamination, increasing cost by 20–50%.

Buried Via

Connects two or more inner layers without reaching the surface. Invisible on outer layers, maximising surface real-estate. Highest-cost option; used in advanced HDI designs for mobile SoCs and fine-pitch BGAs.

Annular ring rule: the copper ring surrounding a via hole must be large enough to guarantee a reliable connection after drill registration tolerance. IPC-2221 Class B requires a minimum annular ring of 0.05 mm (2 mil). Via-in-pad (filling with resin and plating over) allows component placement directly over vias, essential for very fine-pitch BGAs (< 0.5 mm pitch).

19.6 Design Rules, Thermal Management & EMC

Design Rule Checks (DRC)

A DRC verifies that the layout satisfies manufacturing constraints. Key parameters:

Minimum trace width0.1 mm (4 mil)

Minimum clearance0.1 mm (4 mil)

Minimum drill diameter0.2 mm

Annular ring≥ 0.05 mm

Copper to board edge≥ 0.3 mm

Solder mask expansion0.05 mm per side

Thermal Management

High-power components require thermal relief or thermal vias. A copper polygon pour connected to a heatsink pad with a dense via array conducts heat to inner GND planes. The thermal resistance through a via array: \( \theta = L / (n \cdot k_{\text{Cu}} \cdot A_{\text{via}}) \). Thermal vias of 0.3 mm diameter on a 0.6 mm grid achieve ≈ 5 °C/W for a 10×10 mm pad.

EMC Considerations

EMC-clean layout requires: (1) solid, unbroken GND planes with no split beneath high-speed traces; (2) decoupling capacitors (100 nF, 10 nF, 1 nF) placed as close as possible to power pins; (3) return current paths follow signal traces on the adjacent reference plane; (4) clock traces guarded by GND stitching vias; (5) ferrite beads isolate noisy switching regulators from sensitive analog circuitry.

Python: Trace Width & Impedance Calculator

The simulation below (left) applies the IPC-2221 formula to plot required trace width vs current for three copper weights. The centre panel plots microstrip characteristic impedance vs w/h ratio for FR4 and Rogers substrates. The right panel shows resistive power loss vs trace width for a 100 mm trace at different currents.

Python

script.py111 lines

import numpy as np
import matplotlib
matplotlib.use('Agg')
import matplotlib.pyplot as plt

fig, axes = plt.subplots(1, 3, figsize=(18, 6))
fig.patch.set_facecolor('#0a0a1a')

# --- Panel 1: IPC-2221 Trace Width vs Current ---
ax1 = axes[0]

# IPC-2221 formula: W = (I / (k * dT^b))^(1/c) / (1.378 * thickness_mils)
# Simplified empirical: for external traces
# I = 0.048 * dT^0.44 * A^0.725   (A = cross-section area in sq mils)
# A = I / (0.048 * dT^0.44)^(1/0.725)
# W [mils] = A / thickness_mils

current = np.linspace(0.1, 10, 300)
dT = 10  # deg C rise

copper_weights = {'0.5 oz (0.7 mil)': 0.7, '1 oz (1.4 mil)': 1.4, '2 oz (2.8 mil)': 2.8}
colors_cw = ['#34d399', '#22d3ee', '#fbbf24']

for (label, thickness_mils), color in zip(copper_weights.items(), colors_cw):
    area_sq_mils = (current / (0.048 * (dT ** 0.44))) ** (1 / 0.725)
    width_mils = area_sq_mils / thickness_mils
    width_mm = width_mils * 0.0254
    ax1.plot(current, width_mm, color=color, linewidth=2.5, label=label)

ax1.set_xlabel('Current (A)', fontsize=12, color='white')
ax1.set_ylabel('Trace Width (mm)', fontsize=12, color='white')
ax1.set_title('IPC-2221 Trace Width vs Current', fontsize=13, color='white', fontweight='bold')
ax1.legend(fontsize=9, facecolor='#1a1a2e', edgecolor='#34d399', labelcolor='white')
ax1.set_facecolor('#0a0a1a')
ax1.tick_params(colors='white')
ax1.grid(True, alpha=0.2, color='#34d399')
for spine in ax1.spines.values():
    spine.set_color('#34d399')

# --- Panel 2: Microstrip Impedance Z0 vs Width/Height Ratio ---
ax2 = axes[1]

# Z0 = (87 / sqrt(er + 1.41)) * ln(5.98*h / (0.8*w + t))
# Vary w/h ratio, fix er and t/h
er_vals = [4.4, 3.55, 2.2]  # FR4, Rogers 4003, Rogers 4350
er_labels = ['FR4 (er=4.4)', 'Rogers 4003 (er=3.55)', 'Rogers 4350 (er=2.2)']
colors_er = ['#34d399', '#22d3ee', '#a78bfa']
h = 1.0   # normalised height
t = 0.035  # 1 oz copper thickness in mm (typical), normalised

w_over_h = np.linspace(0.05, 4.0, 400)
w = w_over_h * h

for er, label, color in zip(er_vals, er_labels, colors_er):
    Z0 = (87 / np.sqrt(er + 1.41)) * np.log(5.98 * h / (0.8 * w + t))
    Z0 = np.where(Z0 > 0, Z0, np.nan)
    ax2.plot(w_over_h, Z0, color=color, linewidth=2.5, label=label)

ax2.axhline(50, color='#f87171', linestyle='--', linewidth=1.5, label='50 Ohm target')
ax2.axhline(75, color='#fb923c', linestyle='--', linewidth=1.2, label='75 Ohm target')

ax2.set_xlabel('Trace Width / Dielectric Height (w/h)', fontsize=12, color='white')
ax2.set_ylabel('Characteristic Impedance Z₀ (Ω)', fontsize=12, color='white')
ax2.set_title('Microstrip Z₀ vs Geometry', fontsize=13, color='white', fontweight='bold')
ax2.legend(fontsize=8, facecolor='#1a1a2e', edgecolor='#34d399', labelcolor='white')
ax2.set_facecolor('#0a0a1a')
ax2.tick_params(colors='white')
ax2.set_ylim(0, 200)
ax2.grid(True, alpha=0.2, color='#34d399')
for spine in ax2.spines.values():
    spine.set_color('#34d399')

# --- Panel 3: Power dissipation in trace vs width ---
ax3 = axes[2]

# Resistance per unit length: R/L = rho / (w * t)   [Ohm/mm]
# rho_cu = 1.724e-5 Ohm*mm (resistivity)
rho_cu = 1.724e-5  # Ohm*mm

widths_mm = np.linspace(0.1, 3.0, 300)
thickness_mm = 0.035  # 1 oz copper

currents_plot = [0.5, 1.0, 2.0, 4.0]
colors_I = ['#34d399', '#22d3ee', '#fbbf24', '#f87171']

trace_length_mm = 100  # 100 mm trace

for I_val, color in zip(currents_plot, colors_I):
    R = rho_cu * trace_length_mm / (widths_mm * thickness_mm)
    P_mW = I_val ** 2 * R * 1000
    ax3.plot(widths_mm, P_mW, color=color, linewidth=2.5, label=str(I_val) + ' A')

ax3.set_xlabel('Trace Width (mm)', fontsize=12, color='white')
ax3.set_ylabel('Power Dissipation (mW) — 100 mm trace', fontsize=11, color='white')
ax3.set_title('Trace Resistive Loss vs Width', fontsize=13, color='white', fontweight='bold')
ax3.legend(fontsize=9, facecolor='#1a1a2e', edgecolor='#34d399', labelcolor='white', title='Current', title_fontsize=8)
ax3.set_facecolor('#0a0a1a')
ax3.tick_params(colors='white')
ax3.set_ylim(0, 800)
ax3.grid(True, alpha=0.2, color='#34d399')
for spine in ax3.spines.values():
    spine.set_color('#34d399')

plt.tight_layout()
plt.savefig('output.png', dpi=150, bbox_inches='tight', facecolor='#0a0a1a')
plt.show()
print('IPC-2221 trace width calculation complete.')
print('Microstrip Z0 formula: Z0 = (87/sqrt(er+1.41)) * ln(5.98h/(0.8w+t))')
print('For 50-ohm microstrip on FR4 (er=4.4, h=1.6mm, t=0.035mm): w ~ 3.0 mm')
print('Resistivity of copper: 1.724e-8 Ohm*m at 20 deg C')

Click Run to execute the Python code

Code will be executed with Python 3 on the server

Key Equations

IPC-2221 trace current (external):\( I = 0.048 \cdot \Delta T^{0.44} \cdot A^{0.725} \) — A in sq mils, ΔT in °C

Microstrip impedance:\( Z_0 = \dfrac{87}{\sqrt{\varepsilon_r + 1.41}} \ln\!\left(\dfrac{5.98h}{0.8w + t}\right) \)

Trace resistance per length:\( R/L = \rho_{\text{Cu}} / (w \cdot t) \) — ρ_Cu = 1.724×10⁻⁸ Ω·m

Signal wavelength in PCB:\( \lambda = c / (f \sqrt{\varepsilon_r}) \) — control impedance for traces > λ/10

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