Part II: Inside the FPGA
What a field-programmable gate array actually is: look-up tables, flip-flops, programmable routing, and the hard blocks of the Zynq-7020 on the PYNQ-Z2.
The fabric at a glance
What you will learn
Part I built digital logic from gates and flip-flops on paper. Part II opens up the chip that will carry your designs: the Zynq XC7Z020 on the PYNQ-Z2. Chapter 4 places the FPGA among CPUs, GPUs and custom chips and explains how a bitstream turns generic silicon into your circuit. Chapter 5 shows that every piece of logic ends up as a small truth table in a look-up table, next to flip-flops, carry chains and a sea of programmable wires. Chapter 6 covers the hard blocks — block RAM, DSP multipliers, clock synthesisers — and introduces the ARM processors on the same die.
After this part you will be able to look at a line of HDL and predict, roughly, what hardware it becomes and what it costs: how many LUTs, whether it uses the carry chain, a block RAM or a DSP slice, and what limits its speed.
Chapters in Part II
What Is an FPGA?
From PALs and CPLDs to modern FPGAs; FPGA versus CPU, GPU and ASIC; configuration memory and the bitstream; when an FPGA is the right tool.
LUTs, Flip-Flops & Routing
A look-up table is a tiny memory holding a truth table. Slices, configurable logic blocks, carry chains, switch matrices and I/O blocks.
Block RAM, DSP & Clocking
The hard blocks: 36 Kb block RAMs, DSP48E1 multiply–accumulate slices, global clock networks, PLLs and MMCMs — and the ARM processors next door.