Part VII: Hardware Meets Software
The Zynq system-on-chip, the AXI bus, a custom peripheral with registers, and finally Python in a Jupyter notebook driving your own hardware accelerator.
Two halves of one chip
The Zynq on the PYNQ-Z2 is a processor and an FPGA on the same die. The processing system (PS) is a dual-core ARM Cortex-A9 with its DDR memory controller and standard peripherals; it boots Linux and runs Python. The programmable logic (PL) is the fabric you have been designing for since Part II. The two meet at a set of AXI ports: the ARM reaches your registers through the general-purpose (GP) master ports, and your hardware reaches DDR memory through the high-performance (HP) slave ports.
Chapter 19 explains the AXI protocol and its valid/ready handshake. Chapter 20 builds a register-mapped peripheral from scratch. Chapter 21 drives it, and DMA transfers, from a Jupyter notebook with PYNQ. Chapter 22 ends the course with a streaming accelerator and an honest measurement of when hardware beats software — and when it does not.
Chapters in Part VII
The Zynq SoC & the AXI Bus
Processing system and programmable logic, the AXI4 family (AXI-Lite, AXI4, AXI-Stream), valid/ready handshakes and memory-mapped registers.
Building an AXI-Lite Peripheral
A register-mapped peripheral written from scratch, verified in simulation, packaged as IP and wired into a Vivado block design.
Python Drives Hardware: PYNQ Overlays
Bitstreams as Python objects: Overlay, MMIO, interrupts and DMA with contiguous buffers, all from a Jupyter notebook on the board.
Capstone: A Hardware Accelerator
A streaming dot-product engine fed by DMA, measured against NumPy on the ARM cores; when acceleration pays and when it does not; where to go next.